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# File Upload Date Size Tag
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December 31, 1969 0 bytes
1 ADP_JTL_scaling1.jpg
August 11, 2017 57.97KB
2 16-Bit Wave-Pipelined Sparse-Tree RSFQ_Adder.pdf
January 28, 2018 648.63KB
3 20GHz 8x8bit parallel carry_save RSFQ multiplier.pdf
September 2, 2017 576.79KB
4 ERSFQ 8-bit Parallel Arithmetic Logic Unit.pdf
March 3, 2019 636.77KB
5 FFT_Processor_2017.pdf
August 11, 2017 664.35KB
6 Reversibility and energy dissipation in adiabatic superconductor logic.pdf
January 11, 2018 2.84MB
7 Review_Fujimaki_ISEC_2017.pdf
August 11, 2017 2.83MB
8 Signal_Transmission_between_AQFP_and_SFQ_circuits.pdf
August 31, 2017 726.65KB
9 Superconducting Magnetic Field Programmable Gate Array .pdf
February 17, 2018 7.02MB
10 Synthesis flow for AQFP circuits.pdf
August 31, 2017 611.50KB

 

 

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