skip to Main Content
1-631-632-8611 quantarctic@gmail.com
The ABCs Of Flux Quantum Computing In 300 Words Or Less:  VLSI Flux Quantum Circuit Design For Success

The ABCs of Flux Quantum Computing in 300 words or less: VLSI Flux Quantum Circuit Design for Success

VLSI Flux Quantum Circuit Design for Success

Is there any recipe for designing 20 GHz+ superconductor VLSI  flux quantum circuits? After all, despite all the efforts, there are no flux quantum computers yet, and that raises the legitimate question of designability of complex superconductor circuits.

To answer the question we need to understand what makes flux quantum circuits fail. Some will say it is due to immature technology, while other will point to immature CAD tools. While it is true that we could benefit a lot from better technology and better tools, that type of explanation basically shifts the focus (or, some say, blame) from the designer to something beyond his/her control. Instead, as designers, we need to focus on how to maximize our chances for success despite immature technology and tools.

Complex flux quantum circuits fail mostly because of four reasons: 1) small operational margins and 2) timing violations (namely, set-up and hold times) in their gates, 3) the negative impact of the magnetic field created by large bias currents used for powering the circuits, and 4) parasitic flux trapping during chip cooling to cryogenic temperatures.

The design for success starts at the Josephson junction (JJ) level with the goal of developing gate designs with large margins able to tolerate unavoidable fabrication process imperfections and fluctuations in bias currents. At the cell level, designers need to find optimal processing and clocking mechanisms to minimize the possibility of timing violations in the clocked gates. Besides design architecture, their choice of flux quantum logic family (e.g., RSFQ, ERSFQ, or RQL) will have a profound effect on a way how these issues can be addressed in the design. Finally, the chip layout designer needs to employ techniques for mitigating the effects of large bias currents and flux trapping by shielding power distribution networks and placing so-called flux moats around cells.

Can it be done successfully? The photo shows the 20 GHz 8-bit wave-pipelined RSFQ ALU chip with ~8K JJs designed and demonstrated in a joint project of ECE Dept. Stony Brook University and Hypres, Inc. in 2012. The design was fully operational at 20 GHz clock rate from the very first niobium, the feat neither before nor after achieved for any flux quantum chip of that complexity.

Mikhail Dorojevets

Dept. of Electrical and Computer Engineering, Stony Brook University

 

 

 

 

Leave a Reply

Back To Top