The ABCs of Flux Quantum Computing in 300 words or less: Flux Quantum Circuits

Flux Quantum Circuits

The coding of digital information and operation of the flux quantum circuits are based on the property of superconducting loops to quantize magnetic flux. Flux quantum logic cells employ superconducting loops interrupted with Josephson junctions (JJs) playing a role of I/O interface. The cell logical states ‘1’ and ‘0’ are represented by a presence and absence of a single flux quantum, respectively. When output JJs switch during operation, they create very short mV-level SFQ pulses travelling to other cells over active Josephson transmission lines (JTLs) and/or passive Nb transmission lines (PTLs).

Similar to CMOS, flux quantum cells can be either asynchronous (combinational) or synchronous, the latter requiring clock signals to generate output signals. To broadcast pulse clock signals some logic families, such as RSFQ and ERSFQ, use active clock distribution networks built with JTLs, pulse splitters, and PTLs. Other logic families, such as RQL, use four-phase clock & power lines and clock distribution network built with passive elements.

The use of superconducting loops where a signal can be held an unlimited amount of time in a form of circulating current creates a situation when cells can be “contaminated” by the “old” signals from previous cycles. In the flux quantum circuits this issue is resolved by designing cells to be cleaned either by clock signals, or by reset signals requiring additional input ports. In RQL, when generating a logical ‘1’ signal on an output port, every cell generates two output pulses, a positive one used for the logical ‘1,’ and a negative one (a half-cycle later) to reset the cell connected to the output port.

In contrast to CMOS, the interconnect energy consumption does not depend on wire lengths because of the ballistic propagation of pulses with the speed of ~0.1 mm/ps over superconducting Nb PTLs with negligible dielectric losses.

Mikhail Dorojevets

Dept. of Electrical and Computer Engineering, Stony Brook University, NY